1. Field of the Invention
The present invention relates to a logic amplitude level converter circuit which converts an input signal having a low (narrow) logic amplitude of 0-3 V to an output signal having a high (wide) logic amplitude of 0-12 V, and also relates to a liquid-crystal device incorporating the converter circuit on its substrate and an electronic apparatus employing the liquid-crystal device.
2. Description of Related Art
The liquid-crystal panel in an active-matrix type liquid-crystal device (thin-film transistor integrated circuit device) operates from a relatively high operating voltage, and its power supply voltage is about 12 V. An input clock signal of this liquid-crystal panel is supplied by an external timing generator (TG), and the timing generator is typically constructed of a CMOS gate array in which transistors are manufactured in a silicon chip, and its power supply voltage is relatively low, for example, 3V or in a range of 3.3 V-5 V. For this reason, the liquid-crystal panel is typically provided with a built-in logic amplitude level converter circuit which converts an input signal having a low (narrow) logic amplitude of 0-3 V to an output signal having a high (wide) logic amplitude of 0-12 V, and the converter circuit functions as a clock interface.
One of the logic amplitude level converter circuits built in such a liquid-crystal display device is disclosed in Japanese Unexamined Patent Publication No. 6-216753. The logic amplitude level converter circuit, as shown in FIG. 11, comprises detector/offset circuits 1A and 1B, which receive, as their inputs, two-phase clock signals CLK1 and CLK2 having opposite polarities and a low logic amplitude, a level shifter (level converter section) 2 of a differential current mirror circuit which obtains an output clock signal V.sub.out having a high logic amplitude by pulse-amplifying an offset signal, an output inverter 3 of an output-stage buffer circuit for buffering interactions from the subsequent stages, and a constant-current source 4.
Along with the constant-current source 4, P-channel transistors P2 and P6 of the detector/offset circuits 1A and 1B constitute a current mirror circuit, and to flow constant-currents I.sub.A and I.sub.B into N-channel type detection transistors N2 and N6 configured in a diode, the drain voltage of the detection transistors N2 and N6 configured in a diode is necessarily higher than the logic level voltage of the clock signals CLK1 and CLK2 as their source voltage, by an offset voltage (a voltage in excess of a threshold voltage V.sub.th of the detection transistors N2 and N6) V.sub.offset in accordance with constant currents I.sub.A and I.sub.B. If the transistors are beforehand designed such that the threshold voltage V.sub.th of the detection transistors N2 and N6 is equal to the threshold voltage of N-channel input transistors N3 and N5 in the level shifter 2, the gate of the input transistor N3 at its gate will be supplied with the gate voltage (=2+V.sub.offset, for example) which contains the high level of clock signal CLK1 plus the offset voltage even with the high level of the clock signal CLK1 (+2 V, for example) lower than the threshold voltage V.sub.th. For this reason, the input transistor N3 reliably conducts, and since the gate of the input transistor N5 is supplied with the offset voltage only, the input transistor N5 becomes close to its cutoff state. A P-channel load transistor P5 conducts to drive its drain upward to a power supply voltage V.sub.GG (=+12 V).
Since the gate of the input transistor N3 is supplied with the offset voltage V.sub.offset only, with the clock signal CLK1 transited to its low level (0 V), the input transistor N3 comes close to its cutoff state while the input transistor N5 conducts, and the P-channel load transistor P5 cuts off to drive its drain downward to ground voltage V.sub.SS (=0 V).
The output inverter 3, constructed of CMOS inverter, outputs an inverted output clock signal V.sub.out * having a high logic amplitude in response to an output clock signal V.sub.out having a high logic amplitude.
The above conventional logic amplitude level converter circuit has the following disadvantages.
Since the detector transistor N2 has its gate S and drain D connected (in a diode configuration), it always operates in its saturation region, and its voltage-current characteristics are similar to the diode characteristics (a quadratic curve) as shown in FIG. 12. More particularly, supposing I.sub.D represents the drain current, V.sub.DS represents the source-drain voltage, and .beta. represents the current amplification factor, the voltage-current characteristics are EQU I.sub.D =.beta.(V.sub.DS -V.sub.th).sup.2 /2 (1)
Supposing R.sub.on represents the ON-resistance (channel resistance) of the transistor P2 as a current source, the drain current I.sub.D is expressed by the following equation. EQU I.sub.D =.beta.(V.sub.GG -V.sub.DS)/R.sub.on (2)
The offset voltage V.sub.offset corresponds to the intersection in FIG. 12 where the voltage-current characteristics expressed by equation (1) intersects the load line expressed by equation (2). As the ON-resistance R.sub.on of the current source transistor P2 increases, the inclination of the load line decreases, and the offset voltage V.sub.offset draws closer to a value in the vicinity of the threshold voltage V.sub.th from a value larger than the threshold voltage V.sub.th, and since a high-resistance element is difficult to manufacture in a thin-film semiconductor circuit having a thin-film transistor (TFT) as a circuit element in view of utilization of space, high-resistance designs of the ON-resistance of the transistor P2 and variation-free resistance element are also difficult to implement. Since the ON-resistance R.sub.on is generally small, the offset voltage V.sub.offset is set to a value (V.sub.th +v) exceeding the threshold voltage V.sub.th.
When the input clock CLK1 is at a low level (0 V), the offset voltage V.sub.offset is approximately (V.sub.th +v). The gate of the input transistor N3 is constantly supplied with the offset voltage V.sub.offset or greater, causing the level shifter 2 to strongly pulse-amplify the input clock CLK1 at its high-level polarity, in an unbalanced manner. Since the logic threshold value of the pulse-amplified output clock signal V.sub.out is substantially shifted to the low level side, it does not coincide with the logic threshold value of the output inverter 3. Therefore, the duty factor of the inverted output clock signal V.sub.out * output by the output inverter 3 is distorted from the duty factors of the input clocks CLK1 and CLK2.